A semiconductor laser generally has high luminous efficiency and is easily miniaturized. In connection with the development of network communication, a semiconductor laser having mass communication competence and rapid response has been recently demanded in the field of optical communication. For example, in optical communication using an optical fiber, adapting a semiconductor laser to various applications for high power output has been widely studied. Since the conventional optical fiber has a minimum loss wavelength of 1.5 .mu.m, a semiconductor laser emitting light having a wavelength of about 1.5 .mu.m has been mainly used. Among such lasers, a distributed feedback laser (abbreviated as "DFB") including a multiple quantum well (abbreviated as "MQW") configuration in an active layer provides quick response and oscillates in a dynamic single mode, i.e. oscillates at only one wavelength using a pulsed drive, at a low threshold current. Therefore, DFB lasers have been used as semiconductor laser diodes for high response long-distance communication.
One example of a semiconductor laser used for this purpose includes an embedded dielectric layer and is called a ridge type semiconductor laser. The ridge type semiconductor laser has an advantage in that the growth processes are completed in a single step and there are no difficult processes to be controlled, such as diffusion of an impurity and the like.
An exemplary prior process for producing such a semiconductor laser is shown in FIGS. 11A to 20C. Primarily, as shown in FIGS. 11A to 11I, a linear ridge pattern 12 is produced by a technique well known in the art. In FIG. 11A, an active layer 2, comprising multilayers of InP, is formed on a p-InP semiconductor substrate 1, and then a cladding layer 3 of n-InP is formed thereon. Examples of the p-InP semiconductor substrate include a InP semiconductor substrate doped with a Group II element, such as zinc. The impurity concentration in the substrate is preferably equal to or lower than 5.times.10.sup.-18 /cm.sup.3. The thickness of the InP active layer 2 and the cladding layer 3 may be about 0.1 .mu.m and about 1 to 2 .mu.m, respectively. The active layer 2 generally contains no impurity, i.e., is undoped. The cladding layer 3 may be doped with a Group VI element, such as sulfur, in a concentration equal to or lower than 5.times.10.sup.-18 /cm.sup.3.
Then, on the cladding layer 3, a first insulating layer 4 is provided in a stripe-shaped pattern having a width of several microns, preferably a width of 3.0 to 4.0 .mu.m, using a photolithography process (as illustrated in FIG. 11B). The first insulating layer 4 can be an inorganic material, such as SiO.sub.2, SiN, SiON, and the like, which can be formed by a known method. The thickness of the first insulating layer 4 is preferably within the range of from 200 to several thousand angstroms.
A portion of the substrate 1, the active layer 2 and the cladding layer 3 are etched, employing the pattern of the first insulating layer 4 as a mask, to provide a first ridge 11 as shown in FIG. 11C. The substrate 1, as mentioned above, is generally etched to a depth of approximately five microns to decrease the capacitance of the current blocking layer. The depth etched in this step may vary according to the function of the semiconductor device produced.
Subsequently, current blocking layers 5 including multiple semiconductor layers are formed on opposite sides of the first ridge 11, as shown in FIG. 11D. Then the first insulating layer 4 is removed from the first ridge as shown in FIG. 11E. The current blocking layer 5 may be a conventional material, but can be multi-layers of InP doped with a Group II element, such as zinc, in a concentration equal to or lower than 1.times.10.sup.-18 /cm.sup.3, when the layer is p-type. When the layer is n-type, the current blocking layer 5 can be InP doped with a Group II element, such as sulfur, in a concentration equal to or lower than 1.times.10.sup.-18 /cm.sup.3, or InP doped with iron.
FIG. 11F illustrates formation of a contact layer 6 on the first ridge 11 and the current blocking layer 5. An example of an n-type contact layer may comprise InGaAs or InGaAsP doped with a Group II element, such as sulfur, in a concentration equal to or lower than 1.times.10.sup.-19 /cm.sup.3, wherein the thickness of the layer should be lower than one micron.
FIGS. 11G and 11H show that, on the contact layer 6, a second insulating layer 7 is formed, which is etched using photolithography, to produce a second ridge in a stripe-shaped pattern with a width of several microns, more preferably 10 to 15 .mu.m. The second insulating layer 7 may be formed from the same material as the first insulating layer described above. The insulating layers may be the same or different materials.
Both the contact layer 6 and the current blocking layer 5 and a portion of the substrate 1 are etched, using the pattern of the second insulating layer as a mask, to provide the second ridge 12 in a stripe-shaped pattern, preferably having a width of 10 to 15 .mu.m (see FIG. 11H). Similar to the first ridge, the depth etched in this step may vary according to the function of the semiconductor device produced. Thereafter, the second insulating layer 7 is removed from the contact layer as illustrated in FIG. 11I.
Then, as shown in FIGS. 12A and 12B, a space between the second ridge patterns 12 is filled with an organic dielectric layer 38, generally a polyimide. The organic dielectric layer 38 can be produced by applying an organic dielectric material to the substrate 1 and etching in an oxygen ion plasma until the surface of the dielectric layer 38 is flat, in other words, until the surface of the second ridge 12 is exposed.
Subsequently, in the conventional method, a third insulating layer 39 is formed on the organic dielectric layer 38 and on the ridge pattern 12 as shown in FIGS. 13A and 13B. Generally, the third insulating layer 39 may be formed from an inorganic insulating material, for example, SiO.sub.2, SiN, SiON, and the like, by a well-known method, and may preferably have a thickness between 500 and 4,000 .ANG.. The third insulating layer 39 may have a smaller rectangular pattern, e.g., 250 .mu.m.times.250 .mu.m, than the size of the final device so it is confined within the borderline 21, e.g., 300 .mu.m.times.300 .mu.m, as illustrated in FIG. 13A.
The organic dielectric layer 38 is then subjected to dry etching, using the third insulating layer 39 as a mask, in an oxygen asher which uses an oxygen ion plasma for etching, as shown in FIGS. 14A and 14B. After that, the insulating layer 39 is removed, as shown in FIGS. 15A and 15B.
FIGS. 16A and 16B illustrate a surface electrode 40 formed on an exposed surface of the second ridge 12 and the organic dielectric layer 38. Then, a counter electrode 15 is formed on the surface of the substrate 1 opposite the surface having the ridge pattern 12 (see FIG. 17B). As shown in FIGS. 17A and 17B, a semiconductor laser 200 is cut from the wafer along a borderline which comprises an edge parallel to the ridge pattern 12 and another edge corresponding to a cleavage plane, i.e., perpendicular to the former edge, to isolate laser elements from each other.
The semiconductor laser 200 produced by the described conventional method can generate light when a current exceeds a threshold current, depending on the gain of the active layer, upon applying a voltage to the ridge pattern 12 through the electrodes 40 and 15. Between the electrodes 40 and 15, the current blocking layer 5 and the organic dielectric layer 38 constitute a parasitic capacitor of the semiconductor laser device and govern the high speed response of the device, referred to as a high speed pulse response. Accordingly, the semiconductor laser 200 fabricated by the conventional method has a response lower than 60 GHz, when the organic dielectric layer 38 has a low dielectric constant, for example, lower than 1.5, and is located on both sides of the second ridge pattern 12.
In the conventional method, however, it has been found by the present inventors that dry etching rapidly proceeds from the end of the organic dielectric layer 38 along the side of the ridge pattern 12, and that gaps 25 are formed between the ridge pattern 12 and the organic dielectric layer (see FIGS. 18A, 18B, 19A, and 19B). If the gaps 25 are present, in subsequent processing for forming the electrode 40, electrode metal may be deposited not only on the surface of the ridge pattern but on the side thereof as illustrated in FIGS. 20A, 20B, and 20C, which causes problems, such as a short circuit in the device. As a result, productivity is decreased.